H8S2245 datasheet(600/818 Pages) RENESAS

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Section 18 Power-Down Modes

Rev.3.00 Mar. 26, 2007 Page 558 of 772

REJ09B0355-0300

Bit 6

Bit 5

Bit 4

STS2

STS1

STS0

Description

Standby time = 8192 states

(Initial value)

Standby time = 16384 states

Standby time = 32768 states

Standby time = 65536 states

Standby time = 131072 states

Standby time = 262144 states

Reserved

Standby time = 16 states

Bit 3—Output Port Enable (OPE): Specifies whether the output of the address bus and bus

control signals (

CS0 to CS3, AS, RD, HWR, LWR) is retained or set to the high-impedance state

in software standby mode.

Bit 3

OPE

Description

In software standby mode, address bus and bus control signals are high-impedance

In software standby mode, address bus and bus control signals retain output state

(Initial value)

Bits 2 to 0—Reserved: Read-only bits, always read as 0.

18.2.2

System Clock Control Register (SCKCR)

PSTOP

R/W

—

R/W

—

SCK0

R/W

SCK2

R/W

SCK1

R/W

Bit

Initial value

R/W

SCKCR is an 8-bit readable/writable register that performs

φ clock output control and medium-

speed mode control.

SCKCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in

software standby mode.

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