H8S2245 datasheet(746/818 Pages) RENESAS

746 / 818 page

Appendix B Register Field

Rev.3.00 Mar. 26, 2007 Page 704 of 772

REJ09B0355-0300

TCR0—Time Control Register 0

H'FFB0

8-Bit Timer Channel 0

TCR1—Time Control Register 1

H'FFB1

8-Bit Timer Channel 1

CMIEB

R/W

CMIEA

R/W

OVIE

R/W

CCLR1

R/W

CCLR0

R/W

CKS0

R/W

CKS2

R/W

CKS1

R/W

Note: *

Clock input disabled

Internal clock: counted at falling edge

φ/8

Internal clock: counted at falling edge

φ/64

Internal clock: counted at falling edge

φ/8192

For channel 0:

Count at TCNT1 overflow signal*

For channel 1:

Count at TCNT0 compare match A*

External clock: counted at rising edge

External clock: counted at falling edge

External clock: counted at both rising and

falling edges

Clock Select

CMFB interrupt requests (CMIB) are disabled

CMFB interrupt requests (CMIB) are enabled

Compare Match Interrupt Enable B

CMFA interrupt requests (CMIA) are disabled

CMFA interrupt requests (CMIA) are enabled

Compare Match Interrupt Enable A

OVF interrupt requests (OVI) are disabled

OVF interrupt requests (OVI) are enabled

Timer Overflow Interrupt Enable

Clear is disabled

Clear by compare match A

Clear by compare match B

Clear by rising edge of external reset input

Counter Clear

Bit

Initial value

Read/Write

If the count input of channel 0 is the TCNT1 overflow

signal and that of channel 1 is the TCNT0 compare

match signal, no incrementing clock is generated.

Do not use this setting.

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