H8S2245 datasheet(764/818 Pages) RENESAS

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Appendix B Register Field

Rev.3.00 Mar. 26, 2007 Page 722 of 772

REJ09B0355-0300

TSR1—Timer Status Register 1

H'FFE5

TPU1

TCFD

—

TCFU

R/(W)*1

TCFV

R/(W)*1

—

TGFA

R/(W)*1

—

TGFB

R/(W)*1

TCNT counts down

TCNT counts up

Count Direction Flag

Underflow Flag

Overflow Flag

TGRB Capture/Output Compare Flag

[Clearing conditions]

• When DTC is activated by TGIA interrupt while

DISEL bit of MRB in DTC*2 is 0.

• When 0 is written to TGFA after reading

TGFA = 1

TGRA Input Capture/Output Compare Flag

Notes: 1. Can only be written with 0 for flag clearing.

2. DTC can clear this bit only when DISEL is 0 with the transfer counter not being 0.

Bit

Initial value

Read/Write

[Setting conditions]

• When TCNT = TGRA while TGRA is function-

ing as output compare register

• When TCNT value is transferred to TGRA by

input capture signal while TGRA is functioning

as input capture register

[Clearing conditions]

• When DTC*2 is activated by TGIB interrupt while DISEL

bit of MRB in DTC is 0.

• When 0 is written to TGFB after reading TGFB = 1

[Setting conditions]

• When TCNT = TGRB while TGRB is functioning as

output compare register

• When TCNT value is transferred to TGRB by input

capture signal while TGRB is functioning as input

capture register

[Clearing condition]

When 0 is written to TCFV after reading TCFV = 1

[Setting condition]

When the TCNT value overflows (changes from H'FFFF to H'0000 )

[Clearing condition]

When 0 is written to TCFU after reading TCFU = 1

[Setting condition]

When the TCNT value underflows (changes from H'0000 to H'FFFF)

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