H8S2245 datasheet(244/818 Pages) RENESAS

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Section 7 Data Transfer Controller

Rev.3.00 Mar. 26, 2007 Page 202 of 772

REJ09B0355-0300

Table 7.9

Number of States Required for Each Execution Status

Object to be Accessed

On-

Chip

RAM

On-

Chip

ROM

On-

Chip I/O

Registers

External Devices

Bus width

Access states

112

22323

Vector read

—

——

46+2m

3+m

Execution

status

information

read/write

——

—————

Byte data read

112

3+m

Word data read

114

6+2m

3+m

Byte data write

112

3+m

Word data write

114

6+2m

3+m

Internal operation

m: Number of wait states in external device access

The number of execution states is calculated from the formula below. Note that

∑ means the sum

of all transfers activated by one activation event (the number in which the CHNE bit is set to 1,

plus 1).

Number of execution states = I · S

I + ∑ (J · SJ + K · SK + L · SL) + M · SM

For example, when the DTC vector address table is located in on-chip ROM, normal mode is set,

and data is transferred from the on-chip ROM to an internal I/O register, the time required for the

DTC operation is 13 states. The time from activation to the end of the data write is 10 states.

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