HD64F3664FP datasheet(84/444 Pages) RENESAS

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Section 3 Exception Handling

Rev. 6.00 Mar. 24, 2006 Page 56 of 412

REJ09B0142-0600

3.2.4

Interrupt Flag Register 1 (IRR1)

IRR1 is a status flag register for direct transition interrupts, timer A overflow interrupts, and

IRQ3

IRQ0 interrupt requests.

Bit

Bit Name

Initial

Value

R/W

Description

IRRDT

R/W

Direct Transfer Interrupt Request Flag

[Setting condition]

When a direct transfer is made by executing a SLEEP

instruction while DTON in SYSCR2 is set to 1.

[Clearing condition]

When IRRDT is cleared by writing 0

IRRTA

R/W

Timer A Interrupt Request Flag

[Setting condition]

When the timer A counter value overflows

[Clearing condition]

When IRRTA is cleared by writing 0



Reserved

These bits are always read as 1.

IRRI3

R/W

IRQ3 Interrupt Request Flag

[Setting condition]

When

IRQ3 pin is designated for interrupt input and

the designated signal edge is detected.

[Clearing condition]

When IRRI3 is cleared by writing 0

IRRI2

R/W

IRQ2 Interrupt Request Flag

[Setting condition]

When

IRQ2 pin is designated for interrupt input and

the designated signal edge is detected.

[Clearing condition]

When IRRI2 is cleared by writing 0

IRRI1

R/W

IRQ1 Interrupt Request Flag

[Setting condition]

When

IRQ1 pin is designated for interrupt input and

the designated signal edge is detected.

[Clearing condition]

When IRRI1 is cleared by writing 0

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