H8SXSLASH1663 datasheet(457/1158 Pages) RENESAS

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Section 8 Data Transfer Controller (DTC)

Rev.1.00 Jun. 07, 2006 Page 405 of 1102

REJ09B0294-0100

8.2.9

DTC Vector Base Register (DTCVBR)

DTCVBR is a 32-bit register that specifies the base address for vector table address calculation.

Bits 31 to 28 and bits 11 to 0 are fixed 0 and cannot be written to. The initial value of DTCVBR is

H'00000000.

Bit

Bit Name

Initial Value

R/W

Bit

Bit Name

Initial Value

R/W

8.3

Activation Sources

The DTC is activated by an interrupt request. The interrupt source is selected by DTCER. A DTC

activation source can be selected by setting the corresponding bit in DTCER; the CPU interrupt

source can be selected by clearing the corresponding bit in DTCER. At the end of a data transfer

(or the last consecutive transfer in the case of chain transfer), the activation source interrupt flag or

corresponding DTCER bit is cleared.

8.4

Location of Transfer Information and DTC Vector Table

Locate the transfer information in the data area. The start address of transfer information should be

located at the address that is a multiple of four (4n). Otherwise, the lower two bits are ignored

during access ([1:0] = B'00.) Transfer information can be located in either short address mode

(three longwords) or full address mode (four longwords). The DTCMD bit in SYSCR specifies

either short address mode (DTCMD = 1) or full address mode (DTCMD = 0). For details, see

section 3.2.2, System Control Register (SYSCR). Transfer information located in the data area is

shown in figure 8.2

The DTC reads the start address of transfer information from the vector table according to the

activation source, and then reads the transfer information from the start address. Figure 8.3 shows

correspondences between the DTC vector address and transfer information.

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