H8SXSLASH1663 datasheet(463/1158 Pages) RENESAS

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Section 8 Data Transfer Controller (DTC)

Rev.1.00 Jun. 07, 2006 Page 411 of 1102

REJ09B0294-0100

Table 8.3

Chain Transfer Conditions

1st Transfer

2nd Transfer

CHNE CHNS DISEL

Transfer

Counter*

CHNE CHNS DISEL

Transfer

Counter*

DTC Transfer



Not 0



Ends at 1st transfer



Ends at 1st transfer



Interrupt request to CPU



Not 0

Ends at 2nd transfer



Ends at 2nd transfer



Interrupt request to CPU

Not 0



Ends at 1st transfer



Not 0

Ends at 2nd transfer



Ends at 2nd transfer



Interrupt request to CPU

Not 0



Ends at 1st transfer

Interrupt request to CPU

Notes: 1. CRA in normal mode transfer, CRAL in repeat transfer mode, or CRB in block transfer

mode

2. When the contents of the CRAH is written to the CRAL in repeat transfer mode

8.5.1

Bus Cycle Division

When the transfer data size is word and the SAR and DAR values are not a multiple of 2, the bus

cycle is divided and the transfer data is read from or written to in bytes. Similarly, when the

transfer data size is longword and the SAR and DAR values are not a multiple of 4, the bus cycle

is divided and the transfer data is read from or written to in words.

Table 8.4 shows the relationship among, SAR, DAR, transfer data size, bus cycle divisions, and

access data size. Figure 8.5 shows the bus cycle division example.

Table 8.4

Number of Bus Cycle Divisions and Access Size

Specified Data Size

SAR and DAR Values

Byte (B)

Word (W)

Longword (LW)

Address 4n

1 (B)

1 (W)

1 (LW)

Address 2n + 1

1 (B)

2 (B-B)

3 (B-W-B)

Address 4n + 2

1 (B)

1 (W)

2 (W-W)

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