H8SXSLASH1663 datasheet(696/1158 Pages) RENESAS

696 / 1158 page

Section 14 Watchdog Timer (WDT)

Rev.1.00 Jun. 07, 2006 Page 644 of 1102

REJ09B0294-0100

Bit

Bit Name

Initial

Value

R/W

Description

OVF

R/(W)* Overflow Flag

Indicates that TCNT has overflowed in interval timer

mode. Only 0 can be written to this bit, to clear the flag.

[Setting condition]

When TCNT overflows in interval timer mode (changes

from H'FF to H'00)

When internal reset request generation is selected in

watchdog timer mode, OVF is cleared automatically by

the internal reset.

[Clearing condition]

Cleared by reading TCSR when OVF = 1, then writing 0

to OVF

(When the CPU is used to clear this flag by writing 0

while the corresponding interrupt is enabled, be sure to

read the flag after writing 0 to it.)

WT/

R/W

Timer Mode Select

Selects whether the WDT is used as a watchdog timer or

interval timer.

0: Interval timer mode

When TCNT overflows, an interval timer interrupt

(WOVI) is requested.

1: Watchdog timer mode

When TCNT overflows, the

WDTOVF signal is output.

TME

R/W

Timer Enable

When this bit is set to 1, TCNT starts counting. When this

bit is cleared, TCNT stops counting and is initialized to

H'00.

4, 3



All 1

Reserved

These are read-only bits and cannot be modified.

CKS2

CKS1

CKS0

R/W

Clock Select 2 to 0

Select the clock source to be input to TCNT. The overflow

cycle for P

φ = 20 MHz is indicated in parentheses.

000: Clock P

φ/2 (cycle: 25.6 µs)

001: Clock P

φ/64 (cycle: 819.2 µs)

010: Clock P

φ/128 (cycle: 1.6 ms)

011: Clock P

φ/512 (cycle: 6.6 ms)

100: Clock P

φ/2048 (cycle: 26.2 ms)

101: Clock P

φ/8192 (cycle: 104.9 ms)

110: Clock P

φ/32768 (cycle: 419.4 ms)

111: Clock P

φ/131072 (cycle: 1.68 s)

Note:

Only 0 can be written to this bit, to clear the flag.

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