H8SXSLASH1663 datasheet(767/1158 Pages) RENESAS

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Section 15 Serial Communication Interface (SCI, IrDA, CRC)

Rev.1.00 Jun. 07, 2006 Page 715 of 1102

REJ09B0294-0100

15.6

Operation in Clocked Synchronous Mode (SCI_0, 1, 2, and 4 only)

Figure 15.17 shows the general format for clocked synchronous communication. In clocked

synchronous mode, data is transmitted or received in synchronization with clock pulses. One

character in transfer data consists of 8-bit data. In data transmission, the SCI outputs data from one

falling edge of the synchronization clock to the next. In data reception, the SCI receives data in

synchronization with the rising edge of the synchronization clock. After 8-bit data is output, the

transmission line holds the MSB output state. In clocked synchronous mode, no parity bit or

multiprocessor bit is added. Inside the SCI, the transmitter and receiver are independent units,

enabling full-duplex communication by use of a common clock. Both the transmitter and the

receiver also have a double-buffered structure, so that the next transmit data can be written during

transmission or the previous receive data can be read during reception, enabling continuous data

transfer.

Don't care

One unit of transfer data (character or frame)

Bit 0

Serial data

Synchronization

clock

Bit 1

Bit 3

Bit 4

Bit 5

LSB

MSB

Bit 2

Bit 6

Bit 7

Note: * Holds a high level except during continuous transfer.

Figure 15.17 Data Format in Clocked Synchronous Communication (LSB-First)

15.6.1

Clock

Either an internal clock generated by the on-chip baud rate generator or an external

synchronization clock input at the SCK pin can be selected, according to the setting of the CKE1

and CKE0 bits in SCR. When the SCI is operated on an internal clock, the synchronization clock

is output from the SCK pin. Eight synchronization clock pulses are output in the transfer of one

character, and when no transfer is performed the clock is fixed high. Note that in the case of

reception only, the synchronization clock is output until an overrun error occurs or until the RE bit

is cleared to 0. (Setting is prohibited in SCI_5 and SCI_6.)

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