H8SXSLASH1663 datasheet(881/1158 Pages) RENESAS

881 / 1158 page

Section 17 I

2C Bus Interface 2 (IIC2)

Rev.1.00 Jun. 07, 2006 Page 829 of 1102

REJ09B0294-0100

Bit

Bit Name

Initial

Value

R/W

Description

RDRF

R/W

Receive Data Register Full

[Setting condition]

• When receive data is transferred from ICDRS to

ICDRR

[Clearing conditions]

• When 0 is written to this bit after reading RDRF = 1

(When the CPU is used to clear this flag by writing

0 while the corresponding interrupt is enabled, be

sure to read the flag after writing 0 to it.)

• When data is read from ICDRR

NACKF

R/W

No Acknowledge Detection Flag

[Setting condition]

• When no acknowledge is detected from the receive

device in transmission while the ACKE bit in ICIER

is set to 1

[Clearing condition]

• When 0 is written to this bit after reading NACKF =

(When the CPU is used to clear this flag by writing

0 while the corresponding interrupt is enabled, be

sure to read the flag after writing 0 to it.)

STOP

R/W

Stop Condition Detection Flag

[Setting condition]

• When a stop condition is detected after frame

transfer

[Clearing condition]

• When 0 is written to this bit after reading STOP = 1

(When the CPU is used to clear this flag by writing

0 while the corresponding interrupt is enabled, be

sure to read the flag after writing 0 to it.)

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