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H8SX/1663 데이터시트(PDF) 939 Page - Renesas Technology Corp

부품명 H8SX/1663
상세설명  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
PDF  1158 Pages
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제조업체  RENESAS [Renesas Technology Corp]
홈페이지  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

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Section 21 Flash Memory (0.18-
µm F-ZTAT Version)
Rev.1.00 Jun. 07, 2006 Page 887 of 1102
REJ09B0294-0100
Bit
Bit Name
Initial
Value
R/W
Description
0
SCO
0
(R)/W*
Source Program Copy Operation
Requests the on-chip programming/erasing program to
be downloaded to the on-chip RAM. When this bit is set
to 1, the on-chip program which is selected by FPCS or
FECS is automatically downloaded in the on-chip RAM
area specified by FTDAR.
In order to set this bit to 1, the RAM emulation mode
must be canceled, H'A5 must be written to FKEY, and
this operation must be executed in the on-chip RAM.
Dummy read of FCCS must be executed twice
immediately after setting this bit to 1. All interrupts must
be disabled during download. This bit is cleared to 0
when download is completed.
During program download initiated with this bit,
particular processing which accompanies bank-
switching of the program storage area is executed.
Before a download request, initialize the VBR contents
to H'00000000. After download is completed, the VBR
contents can be changed.
0: Download of the programming/erasing program is
not requested.
[Clearing condition]
• When download is completed
1: Download of the programming/erasing program is
requested.
[Setting conditions] (When all of the following conditions
are satisfied)
• Not in RAM emulation mode (the RAMS bit in
RAMER is cleared to 0)
• H'A5 is written to FKEY
• Setting of this bit is executed in the on-chip RAM
Note:
*
This is a write-only bit. This bit is always read as 0.



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