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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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H8SX/1663 데이터시트(PDF) 315 Page - Renesas Technology Corp |
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H8SX/1663 데이터시트(HTML) 315 Page - Renesas Technology Corp |
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315 / 1158 page  Section 6 Bus Controller (BSC) Rev.1.00 Jun. 07, 2006 Page 263 of 1102 REJ09B0294-0100 6.11.8 Controlling Precharge Cycle When the time between the PALL or PRE command and the subsequent ACTV or REF command does not meet a given specification, the Tp cycles can be extended by one to four cycles by bits TPC1 and TPC0 in DRACCR. Set the bit according to the SDRAM to be used and the frequency of this LSI so that the number of Tp cycles can be optimal. Figures 6.65 and 6.66 show a timing example when the two Tp cycles are inserted. Bits TPC1 and TPC0 are effective for the Tp cycle in a refresh cycle. T p1 T p2 T r T c1 T cl T c2 Address bus Row address Column address SD φ CS Precharge-sel RAS CAS WE CKE PALL ACTV READ NOP NOP DQMLU DQMLL D7 to D0 BS RD/ WR D15 to D8 Row address High Figure 6.65 Read Timing Example of Two Precharge Cycles (TPC1 = 0, TPC0 = 1, CAS Latency = 2) |
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