H8SXSLASH1663 datasheet(324/1158 Pages) RENESAS

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Section 6 Bus Controller (BSC)

Rev.1.00 Jun. 07, 2006 Page 272 of 1102

REJ09B0294-0100

(2) RAS Down Mode

Set the RCDM and BE bits in DRAMCR to 1 to make a transition to the RAS down mode. The

RCDM bit is enabled only when the BE bit is set to 1.

Even if the fast-page mode is selected, the DRAM space is not consecutively accessed and other

spaces may be accessed. The

RAS signal can be held low during other space accesses. Similarly to

the DRAM RAS down mode, the READ or WRIT command can be issued without the ACTV

command. However, two DQM cycles are always inserted for a SDRAM read cycle.

Figures 6.74 and 6.75 show a timing example of RAS down mode.

The next cycle after one of the following conditions is satisfied is a full access cycle.

• When a refresh cycle is performed during RAS down mode

• When a self-refresh is performed

• When a transition to software standby mode is made

• When the external bus requested by the BREQ signal is released

• When either the RCDM or BE bit is cleared to 0

• When setting the SDRAM mode register

Some SDRAMs have a limitation on the time to hold each bank active. When such SDRAM is in

use, if the user program cannot control the time (such as software standby or sleep mode), select

the auto-refresh or self-refresh so that the given specification can be satisfied. If a refresh cycle is

not used, the user program must control the time.

Clear the RCDM bit to 0 for write access to SCKCR to set the clock frequencies. For SCKCR, see

section 22, Clock Pulse Generator.

(3) RAS Up Mode

Clear the RCDM bit in DRAMCR to 0 to set the RAS up mode.

Whenever a SDRAM space access is halted and other spaces are accessed, the next cycle is the

PALL command cycle. Only when the SDRAM space continues to be accessed, the fast-page

mode access is performed.

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