H83024 datasheet(39/841 Pages) RENESAS

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Section 1 Overview

Rev. 2.00 Sep 20, 2005 page 1 of 800

REJ09B0260-0200

Section 1 Overview

1.1

Overview

The H8/3024 Group is a series of microcontrollers (MCUs) that integrate system supporting

functions together with an H8/300H CPU core having an original Renesas Technology

architecture.

The H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general registers, and a

concise, optimized instruction set designed for speed. It can address a 16-Mbyte linear address

space. Its instruction set is upward-compatible at the object-code level with the H8/300 CPU,

enabling easy porting of software from the H8/300 Series.

The on-chip system supporting functions include ROM, RAM, a 16-bit timer, an 8-bit timer, a

programmable timing pattern controller (TPC), a watchdog timer (WDT), a serial communication

interface (SCI), an A/D converter, a D/A converter, I/O ports, and other facilities.

The four members of the H8/3024 Group are the H8/3024F-ZTAT, H8/3026F-ZTAT, H8/3024

(mask ROM version), and H8/3026 (mask ROM version).

Seven MCU operating modes offer a choice of bus width and address space size. The modes

(modes 1 to 7) include two single-chip modes and five expanded modes.

In addition to its mask ROM versions, the H8/3024 Group has F-ZTAT™* versions with on-chip

flash memory that allows programs to be freely rewritten by the user. This version enables users to

respond quickly and flexibly to changing application specifications, growing production volumes,

and other conditions.

Table 1.1 summarizes the features of the H8/3024 Group.

Note: * F-ZTAT

TM (Flexible ZTAT) is a trademark of Renesas Technology Corp.

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