M32CSLASH86 datasheet(353/505 Pages) RENESAS

353 / 505 page

Page 330

23. CAN Module

)

(

CANi Time Stamp Register (i=0, 1)

Symbol

Address

After Reset(1)

C0TSR

020916 - 020816

000016

C1TSR

028916 - 028816

000016

Function

Value of time stamp

b15

NOTES:

1. Value is obtained by setting the SLEEP bit in the CiSLPR register to "1" (sleep mode exited) after

reset and supplying the clock to the CAN module.

23.1.8 CANi Time Stamp Register (CiTSR Register) (i=0, 1)

Figure 23.10 C0TSR and C1TSR Registers

The CiTSR register is a 16-bit counter. The TSPRE1 and TSPRE0 bits in the CiCTLR0 register select

the CAN bus bit clock divided by 1, 2, 3 or 4 as the count source for the CiTSR register.

When data transmission or reception is completed, the value of the CiTSR register is automatically

stored into the message slot.

In loopback mode, when either data frame receive message slot or remote frame receive message

slot is available to store the message, the value of the CiTSR register is also stored into the message

slot when data reception is completed. The value of the CiTSR register is not stored when data

transmission is completed.

The CiTSR register starts a counter increment when the RESET1 and RESET0 bits in the CiCTLR0

The CiTSR register is set to "000016":

• at the next count timing after the CiTSR register is set to "FFFF16";

• when the RESET1 and RESET0 bits are set to "1" (CAN module reset) by program; or

• when the TSRESET bit is set to "1" (CiTSR register reset) by program.

CAN bus bit clock =

CAN bit time

M32C/86 데이터시트(PDF) 353 Page - Renesas Technology Corp