M32CSLASH86 datasheet(64/505 Pages) RENESAS

64 / 505 page

Page 41

5. Reset

)

(

5.5 Internal Space

Figure 5.4 shows CPU register states after reset. Refer to 4. SFR for SFR states after reset.

b15

b23

0016

000016

00000016

Contents of addresses

FFFFFE16 to FFFFFC16

Data Register (R0H/R0L)

Address Register (A0)

Static Base Register (SB)

Frame Base Register (FB)

User Stack Pointer (USP)

Interrupt Stack Pointer (ISP)

Interrupt Table Register (INTB)

Program Counter (PC)

General Registers

b15

Flag Register (FLG)

IPL

U I O B S Z D C

X 0 0 0 X X X X 0 0 0 0 0 0 0 0

0016

Data Register (R2)

Data Register (R3)

Address Register (A1)

Data Register (R1H/R1L)

High-Speed Interrupt Registers

b15

b23

XXXX16

XXXXXX16

DMAC-Associated Registers

b23

0016

b15

Flag Save Register (SVF)

PC Save Register (SVP)

Vector Register (VCT)

DMA Mode Register (DMD0)

DMA Transfer Count Register (DCT0)

DMA Transfer Count Reload Register (DRC0)

DMA Memory Address Register (DMA0)

DMA SFR Address Register (DSA0)

DMA Memory Address Reload Register (DRA0)

DMA Mode Register (DMD1)

DMA Transfer Count Register (DCT1)

DMA Transfer Count Reload Register (DRC1)

DMA Memory Address Register (DMA1)

DMA SFR Address Register (DSA1)

DMA Memory Address Reload Register (DRA1)

0016

XXXX16

XXXXXX16

0 : "0" after reset

X : Indeterminate after reset

Figure 5.4 CPU Register States after Reset

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