SH7727 datasheet(28/1109 Pages) RENESAS

28 / 1109 page

Rev. 5.00 Dec 12, 2005 page xxviii of lxxii

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Previous Version

Revised Version

949

Figure 32.17 Basic Bus Cycle (External

Wait, WAITSEL = 1)

D31 to D0

(read)

tRDS1

Figure 32.19 Basic Bus Cycle (External

Wait, WAITSEL = 1)

D31 to D0

(read)

tRDS1

Note added

Notes: tRDH1: Specified based on the earliest negate timing of CSn or RD.

tAH:

Specified based on the latest negate timing of

CSn, RD, or WEn.

971

Table 32.8 Peripheral Module Signal

Timing

–66.67

Min

Max

Table 32.11 Peripheral Module Signal

Timing

Min

Max

Note: * Pcyc stands for “P clock cycle.”

Note: * Pcyc stands for “peripheral clock

φ) cycle.”

973

Figure 32.42 I/O Port Timing

PORT 7 to 0

(read)

(B:P clock ratio = 1:1)

PORT 7 to 0

(write)

PORT 7 to 0

(read)

(B:P clock ratio = 1:4)

PORT 7 to 0

(read)

(B:P clock ratio = 1:2)

Figure 32.44 I/O Port Timing

PORT A to H,

J to M, SC (write)

PORT A to H,

J to M, SC (read)

(bus clock:peripheral

clock ratio = 1:1)

PORT A to H,

J to M, SC (read)

(bus clock:peripheral

clock ratio = 1:1/4)

PORT A to H,

J to M, SC (read)

(bus clock:peripheral

clock ratio = 1:1/2)

974

Figure 32.45 TCK Input Timing

tTCKL

tTCKf

VIL VIL

VIH

VIL

1/2VccQ

tTCKf

tTCKH

tTCKcyc

TCK (input)

Note: When clock is input from TCK pin

Figure 32.47 TCK Input Timing

tTCKL

tTCKf

VIL VIL

VIH

1/2 VccQ

tTCKf

tTCKH

tTCKcyc

TCK (input)

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