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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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SH7124 데이터시트(PDF) 49 Page - Renesas Technology Corp |
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SH7124 데이터시트(HTML) 49 Page - Renesas Technology Corp |
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49 / 774 page  Section 2 CPU Rev. 4.00 Jul. 25, 2008 Page 29 of 750 REJ09B0243-0400 Addressing Mode Instruction Format Effective Address Calculation Method Calculation Formula PC relative Rn Effective address is sum of PC and Rn. PC PC + Rn Rn + PC + Rn Immediate #imm:8 8-bit immediate data imm of TST, AND, OR, or XOR instruction is zero-extended. #imm:8 8-bit immediate data imm of MOV, ADD, or CMP/EQ instruction is sign-extended. #imm:8 8-bit immediate data imm of TRAPA instruction is zero-extended and multiplied by 4. 2.4.3 Instruction Formats This section describes the instruction formats, and the meaning of the source and destination operands. The meaning of the operands depends on the instruction code. The following symbols are used in the table. xxxx: Instruction code mmmm: Source register nnnn: Destination register iiii: Immediate data dddd: Displacement |
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