H83502 datasheet(73/386 Pages) RENESAS

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Section 4 Exception Handling

4.1

Overview

The H8/3502 recognizes only two kinds of exceptions: interrupts and the reset. Table 4-1 indicates

their priority and the timing of their hardware exception-handling sequence.

Table 4-1

Reset and Interrupt Exceptions

Priority

Type of

Exception

Detection

Timing

Timing of Exception-Handling Sequence

High

Low

Reset

Interrupt

Clock

synchronous

On completion

of instruction

execution*

When

RES goes low, the chip enters the reset

state immediately. The hardware exception-

handling sequence (reset sequence) begins as

soon as

RES goes high again.

When an interrupt is requested, the hardware

exception-handling sequence (interrupt sequence)

begins at the end of the current instruction, or at

the end of the current hardware exception-handling

sequence.

Note:

* Not detected in case of ANDC, ORC, XORC, and LDC instructions.

4.2

Reset

4.2.1

Overview

A reset has the highest exception-handling priority. When the

RES pin goes low or a watchdog

reset is started (watchdog timer overflow for which the reset option is selected), all current

processing stops and the chip enters the reset state. The internal state of the CPU and the registers

of the on-chip supporting modules are initialized. When

RES returns from low to high or the

watchdog reset pulse ends, the chip comes out of the reset state via the reset exception-handling

sequence.

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