SH7050 datasheet(86/841 Pages) RENESAS

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Section 5 Exception Processing

Rev. 5.00 Jan 06, 2006 page 66 of 818

REJ09B0273-0500

5.3

Address Errors

5.3.1

Address Error Sources

Address errors occur when instructions are fetched or data read or written, as shown in table 5.5.

Table 5.5

Bus Cycles and Address Errors

Bus Cycle

Type

Bus

Master

Bus Cycle Description

Address Errors

Instruction fetched from even address

None (normal)

Instruction

fetch

CPU

Instruction fetched from odd address

Address error occurs

Instruction fetched from other than on-chip

peripheral module space*

None (normal)

Instruction fetched from on-chip peripheral

module space*

Address error occurs

Instruction fetched from external memory space

when in single chip mode

Address error occurs

Word data accessed from even address

None (normal)

Data

read/write

CPU or

DMAC

Word data accessed from odd address

Address error occurs

Longword data accessed from a longword

boundary

None (normal)

Longword data accessed from other than a

long-word boundary

Address error occurs

Byte or word data accessed in on-chip

peripheral module space*

None (normal)

Longword data accessed in 16-bit on-chip

peripheral module space*

None (normal)

Longword data accessed in 8-bit on-chip

peripheral module space*

Address error occurs

External memory space accessed when in

single chip mode

Address error occurs

Note:

See section 8, Bus State Controller.

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