7534 datasheet(59/221 Pages) RENESAS

59 / 221 page

HARDWARE

7534 Group

Rev.3.00

Oct 23, 2006

page 46 of 55

REJ09B0178-0300

Timing After Interrupt

The interrupt processing routine begins with the

machine cycle following the completion of the

instruction that is currently in execution.

Figure 52 shows a timing chart after an interrupt

occurs, and Figure 53 shows the time up to execution

of the interrupt processing routine.

Fig. 52 Timing chart after an interrupt occurs

Fig. 53 Time up to execution of the interrupt processing routine

: CPU operation code fetch cycle

: Vector address of each interrupt

: Jump destination address of each interrupt

: “0016” or “0116”

SYNC

BL, BH

AL, AH

SPS

Data bus

Not used

PCH

PCL

Address bus

S, SPS

S-2, SPS

S-1, SPS

AL, AH

SYNC

Generation of interrupt request

Main routine

Interrupt processing routine

7 to 14 cycles

(At performing 6.0 MHz, in double-speed mode,

1.17

µs to 2.34 µs)

2 cycles

5 cycles

Start of interrupt processing

0 to 7 cycles

Waiting time for

post-processing

of pipeline

Stack push and

Vector fetch

FUNCTIONAL DESCRIPTION SUPPLEMENT

7534 데이터시트(PDF) 59 Page - Renesas Technology Corp

7534 데이터시트(HTML) 59 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL