7641_06 datasheet(13/385 Pages) RENESAS

13 / 385 page

Rev.2.00

Aug 28, 2006

page 9 of 13

7641 Group

REJ09B0336-0200

Fig. 2.12.8 Connection diagram .................................................................................................. 141

Fig. 2.12.9 Status transition diagram during power failure ..................................................... 141

Fig. 2.12.10 Setting of relevant registers .................................................................................. 142

Fig. 2.12.11 Control procedure ................................................................................................... 143

Fig. 2.12.12 Structure of clock counter ...................................................................................... 144

Fig. 2.12.13 Initial setting of relevant registers ........................................................................ 145

Fig. 2.12.14 Setting of relevant registers after detecting power failure ................................ 146

Fig. 2.12.15 Control procedure (1) ............................................................................................. 147

Fig. 2.12.16 Control procedure (2) ............................................................................................. 148

CHAPTER 3 APPENDIX

Fig. 3.1.1 Circuit for measuring output switching characteristics (1) ...................................... 16

Fig. 3.1.2 Circuit for measuring output switching characteristics (2) ...................................... 16

Fig. 3.1.3 Timing diagram (1) ........................................................................................................ 17

Fig. 3.1.4 Timing diagram (2) ........................................................................................................ 18

Fig. 3.1.5 Timing diagram (3) ........................................................................................................ 18

Fig. 3.1.6 Timing diagram (4) ........................................................................................................ 19

Fig. 3.1.7 Timing diagram (5) ........................................................................................................ 20

Fig. 3.1.8 Timing diagram (6); Memory expansion and microprocessor modes .................... 21

Fig. 3.1.9 Timing diagram (7); Memory expansion and microprocessor modes .................... 22

Fig. 3.2.1 Power source current standard characteristics (Ta = 25 °C) ................................. 23

Fig. 3.2.2 CMOS output port P-channel side characteristics (Ta = 25 °C) ............................ 24

Fig. 3.2.3 CMOS output port P-channel side characteristics (Ta = 70 °C) ............................ 24

Fig. 3.2.4 CMOS output port N-channel side characteristics (Ta = 25 °C) ........................... 25

Fig. 3.2.5 CMOS output port N-channel side characteristics (Ta = 70 °C) ........................... 25

Fig. 3.2.6 Port P20–P27 at pull-up characteristics (Ta = 25 °C) .............................................. 26

Fig. 3.2.7 Port P20–P27 at pull-up characteristics (Ta = 70 °C) .............................................. 26

Fig. 3.3.1 Sequence of setting external interrupt active edge ................................................. 27

Fig. 3.3.2 Circuit example for the proper positions of the peripheral components ............. 33

Fig. 3.3.3 Passive components near LPF pin ........................................................................... 33

Fig. 3.3.4 Insulation connector connection ................................................................................ 33

Fig. 3.3.5 Initialization of processor status register ................................................................... 40

Fig. 3.3.6 Sequence of PLP instruction execution ..................................................................... 41

Fig. 3.3.7 Stack memory contents after PHP instruction execution ........................................ 41

Fig. 3.4.1 Wiring for the RESET pin ............................................................................................ 44

Fig. 3.4.2 Wiring for clock I/O pins .............................................................................................. 44

Fig. 3.4.3 Bypass capacitor across the Vss line and the Vcc line .......................................... 45

Fig. 3.4.4 Wiring for a large current signal line ......................................................................... 46

Fig. 3.4.5 Wiring for signal lines where potential levels change frequently ........................... 46

Fig. 3.4.6 VSS pattern on the underside of an oscillator ......................................................... 47

Fig. 3.4.7 Setup for I/O ports ........................................................................................................ 47

Fig. 3.4.8 Watchdog timer by software ........................................................................................ 48

Fig. 3.5.1 Structure of CPU mode register A ............................................................................. 49

Fig. 3.5.2 Structure of CPU mode register B ............................................................................. 49

Fig. 3.5.3 Structure of Interrupt request register A .................................................................... 50

Fig. 3.5.4 Structure of Interrupt request register B .................................................................... 50

Fig. 3.5.5 Structure of Interrupt request register C ................................................................... 51

Fig. 3.5.6 Structure of Interrupt control register A ..................................................................... 51

Fig. 3.5.7 Structure of Interrupt control register B ..................................................................... 52

Fig. 3.5.8 Structure of Interrupt control register C ..................................................................... 52

Fig. 3.5.9 Structure of Port Pi ....................................................................................................... 53

List of figures

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