SH7750 datasheet(21/1162 Pages) RENESAS

21 / 1162 page

Rev.7.00 Oct. 10, 2008 Page xxi of lxxxiv

REJ09B0366-0700

Item

Page

Revision (See Manual for Details)

13.3.5 Synchronous

DRAM Interface

Figure 13.42 (2)

Synchronous DRAM

Mode Write Timing

(Mode Register Set)

491

Figure amended

CASS

D63–D0

CKE

(High)

Connecting a 128-

Mbit/256-Mbit

Synchronous DRAM

with 64-bit Bus Width

(SH7750R Only):

494, 495 Description amended

• In the auto-refresh operation, the REF command is issued

twice continuously in response to a single refresh request.

The interval cycle number between the first and second REF

commands issuance is specified by the setting of the

TRAS2

−TRAS0 bits in MCR, which is 4 to 11 CKIO cycles.

The interval cycle number between the second REF

command and the next ACTV command issuance is specified

by the settings of both the TRAS2

−TRAS0 bits and the

TRC2

−TRC0 bits in MCR in the sum total, which is 4 to 32

CKIO cycles. Set RTCOR and bits CKS2

−CKS0, and MCR so

as to satisfy the refresh-interval rating of the synchronous

DRAM which you are using. The synchronous DRAM auto-

refresh timing with 64-bit bus width is shown below figure.

Figure 13.46

Synchronous DRAM

Auto-Refresh Timing

with 64-Bit Bus Width

(TRAS [2:0] = 001, TRC

[2:0] = 001))

496

Figure newly added

13.3.7 PCMCIA

Interface

Figure 13.51 Basic

Timing for PCMCIA

Memory Card Interface

505

Figure amended

D15–D0

(write)

WE1

(write)

Figure 13.52 Wait

Timing for PCMCIA

Memory Card Interface

506

Figure amended

D15–D0

(write)

WE1

(write)

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