SH7785 datasheet(21/1692 Pages) RENESAS

21 / 1692 page

Rev.1.00 Jan. 10, 2008 Page xxi of xxx

REJ09B0261-0100

19.4.12 Scroll Display ..................................................................................................... 950

19.4.13 Wraparound Display ........................................................................................... 951

19.4.14 Upper-Left Overflow Display............................................................................. 952

19.4.15 Double Buffer Control ........................................................................................ 953

19.4.16 Sync Mode .......................................................................................................... 954

19.5

Display Control.................................................................................................................. 956

19.5.1

Display Timing Generation ................................................................................ 956

19.5.2

CSYNC ............................................................................................................... 959

19.5.3

Scan Method ....................................................................................................... 961

19.5.4

Color Detection................................................................................................... 965

19.5.5

Output Signal Timing Adjustment...................................................................... 966

19.5.6

CLAMP Signal and DE Signal ........................................................................... 967

19.6

Power-Down Sequence ...................................................................................................... 968

19.6.1

Procedures before Executing the Power-Down Sequence .................................. 968

19.6.2

Resetting the Power-Down Sequence ................................................................. 968

Section 20 Graphics Data Translation Accelerator (GDTA) ................................... 969

20.1

Features.............................................................................................................................. 969

20.2

GDTA Address Space........................................................................................................ 973

20.3

Register Descriptions ......................................................................................................... 974

20.3.1

GA Mask Register (GACMR) ............................................................................ 979

20.3.2

GA Enable Register (GACER) ........................................................................... 980

20.3.3

GA Interrupt Source Indicating Register (GACISR) .......................................... 981

20.3.4

GA Interrupt Source Indication Clear Register (GACICR) ................................ 982

20.3.5

GA Interrupt Enable Register (GACIER) ........................................................... 983

20.3.6

GA CL Input Data Alignment Register (DRCL_CTL)....................................... 984

20.3.7

GA CL Output Data Alignment Register (DWCL_CTL)................................... 985

20.3.8

GA MC Input Data Alignment Register (DRMC_CTL) .................................... 986

20.3.9

GA MC Output Data Alignment Register (DWMC_CTL)................................. 987

20.3.10 GA Buffer RAM 0 Data Alignment Register (DCP_CTL)................................. 988

20.3.11 GA Buffer RAM 1 Data Alignment Register (DID_CTL) ................................. 989

20.3.12 CL Command FIFO (CLCF) .............................................................................. 990

20.3.13 CL Control Register (CLCR).............................................................................. 991

20.3.14 CL Status Register (CLSR)................................................................................. 993

20.3.15 CL Frame Width Setting Register (CLWR) ....................................................... 994

20.3.16 CL Frame Height Setting Register (CLHR) ....................................................... 995

20.3.17 CL Input Y Padding Size Setting Register (CLIYPR)........................................ 996

20.3.18 CL Input UV Padding Size Setting Register (CLIUVPR) .................................. 997

20.3.19 CL Output Padding Size Setting Register (CLOPR) .......................................... 998

20.3.20 CL Palette Pointer Register (CLPLPR) .............................................................. 999

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