M16CSLASH26 datasheet(63/239 Pages) RENESAS

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Interrupts

Renesas Technology Corp.

M16C/26 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Under

development

Preliminary Specifications Rev. 0.9

Specifications in this manual are tentative and subject to change.

Interrupt Priority

If there are two or more interrupt requests generated at the same time, the interrupt assigned with a higher

priority is accepted.

Assign an arbitrary priority to maskable interrupts (peripheral I/O interrupts) using the interrupt priority level

select bit. If the same interrupt priority level is assigned, however, the interrupt assigned with a higher

hardware priority is accepted.

Priorities for the special interrupts, such as reset (dealt with as an interrupt assigned the highest priority),

watchdog timer interrupt, etc. are controlled by hardware.

Figure 1.9.8 shows the priorities of hardware interrupts.

Software interrupts are not affected by the interrupt priority. If an instruction is executed, control branches

invariably to the interrupt routine.

Returning from an Interrupt Routine

Executing a REIT instruction at the end of an interrupt routine returns the contents of the flag register (FLG)

as it was immediately before the start of interrupt sequence and the contents of the program counter (PC),

both of which have been saved in the stack area. Then control returns to the program that was being

executed before the acceptance of the interrupt request, so that the suspended process resumes.

To return the other registers saved by software within the interrupt routine, use the POPM or similar instruc-

tion before executing the REIT instruction.

Interrupt resolution circuit

When two or more interrupts are generated simultaneously, the circuit in Figure 1.9.9 selects the interrupt

based on the priority level shown.

Figure 1.9.8. Hardware interrupts priorities

Reset > NMI > DBC > Watchdog timer > Peripheral I/O > Single step > Address match

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