M16CSLASH26 datasheet(157/239 Pages) RENESAS

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Serial Interface Special Function

151

Renesas Technology Corp.

M16C/26 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Under

development

Preliminary Specifications Rev. 0.9

Specifications in this manual are tentative and subject to change.

• Clock Phase Setting

With bit 1 of UART2 special mode register 3 (addresses 036D16, 037116 and 037516) and bit 6 of

UART2 transmission-reception control register 0 (addresses 03A416, 02AC16 and 037C16), four com-

binations of transfer clock phase and polarity can be selected.

Bit 6 of UART2 transmission-reception control register 0 sets transfer clock polarity, whereas bit 1 of

U2SMR3 register sets transfer clock phase.

Transfer clock phase and polarity must be the same between the master and slave involved in the

transfer.

(a) Master (Internal Clock)

Figure 1.15.33 shows the transmission and reception timing.

(b) Slave (External Clock)

• Figure 1.15.34 shows the timing when bit 1 of address 037516)=“0”

• Figure 1.15.35 shows the timing when bit 1 of address037516)=“1”

Data output timing

Data input timing

Clock output

(CKPOL=0, CKPH=0)

"H"

"L"

Clock output

(CKPOL=1, CKPH=0)

"H"

"L"

Clock output

(CKPOL=0, CKPH=1)

"H"

"L"

Clock output

(CKPOL=1, CKPH=1)

"H"

"L"

"H"

"L"

Figure 1.15.33. The transmission and reception timing in master mode (internal clock)

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