M16CSLASH62 datasheet(487/615 Pages) RENESAS

487 / 615 page

Multiple Interrupts

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

2-170

Figure 2.14.5. Interrupts resolution circuit

Timer B2

Timer B0

Timer A3

Timer A1

Timer B1

Timer A4

Timer A2

UART1 reception

UART0 reception

UART2 reception/ACK

A-D conversion

DMA1

Bus collision detection

Timer A0

UART1 transmission

UART0 transmission

UART2 transmission/NACK

Key input interrupt

DMA0

Processor interrupt priority level (IPL)

Interrupt enable flag (I flag)

INT1

INT2

INT0

Watchdog timer

Reset

DBC

NMI

Interrupt

request

accepted

Level 0 (initial value)

Priority level of each interrupt

High

Low

Priority of peripheral I/O interrupts

(if priority levels are same)

Timer B4

INT3

Timer B3

Timer B5

Serial I/O4/INT5

Serial I/O3/INT4

Address match

Interrupt request level judgment output

to clock generating circuit (Fig.1.10.3)

(6) Interrupt resolution circuit

When two or more interrupts are generated simultaneously, this circuit selects the interrupt with the

highest priority level. Figure 2.14.5 shows the circuit that judges the interrupt priority level.

M16C/62 데이터시트(PDF) 487 Page - Renesas Technology Corp

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