SH7243 datasheet(39/1726 Pages) RENESAS

39 / 1726 page

Section 1 Overview

Rev. 1.00 Jun. 26, 2008 Page 9 of 1692

REJ09B0393-0100

1.2

Block Diagram

SH-2A

CPU core

On-chip RAM

On-chip ROM

User break

controller (UBC)

Bus state

controller

(BSC)

Peripheral

bus controller

Direct memory

access controller

(DMAC)

Pin function

controller

(PFC)

I/O

ports

Clock pulse

generator

(CPG)

Interrupt

controller

(INTC)

Multi-function

timer pulse

unit 2S

(MTU2S)

Multi-function

timer pulse

unit 2

(MTU2)

Port output

enable 2

(POE2)

Compare

match

timer

(CMT)

Internal bus (B clock)

Peripheral bus (P clock)

Watchdog

timer

(WDT)

Serial

communication

interface

(SCI)

Synchronous

serial

communication

interface

(SSU)

Serial

communication

interface

with FIFO

(SCIF)

I2C bus

interface 3

(IIC3)

12-bit A/D

converter

(ADC)

Power-down

mode

control

User debugging

interface

(H-UDI)

CPU instruction fetch bus (F bus)

CPU bus

(C bus)

(I clock)

CPU memory access bus (M bus)

Data transfer

controller

(DTC)

Controller

area network

(RCAN-ET)

D/A

converter

(DAC)

Universal

serial bus

(USB) *1

Notes:

Only in SH7286 and SH7285

Only in SH7286

Figure 1.1 Block Diagram

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