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2.2 Interrupts

APPLICATION

2–19

3825 GROUP USER’S MANUAL

An interrupt request bit, an interrupt enable bit and an interrupt disable flag function independently and do

not affect each other. An interrupt is accepted when all the following conditions are satisfied.

qInterrupt request bit — “1”

qInterrupt enable bit — “1”

qInterrupt disable flag — “0”

Though the interrupt priority is determined by software, a variety of priority processing can be performed

by software using the above bits and flag.

Table 2.2.2 shows a list of interrupt bits for individual interrupt sources.

(1) Interrupt request bits

The interrupt request bits are allocated to the interrupt request register 1 (address 003C16) and

interrupt request register 2 (address 003D16).

The occurrence of an interrupt request causes the corresponding interrupt request bit to be set to “1.”

The interrupt request bit is held in the “1” state until the interrupt is accepted. When the interrupt is

accepted, this bit is automatically cleared to “0.”

Each interrupt request bit can be set to “0” by software, but it cannot be set to “1” by software.

Fig. 2.2.5 Interrupt control diagram

2.2.2 Control

For interrupts except the BRK instruction interrupt, the acceptance of interrupt can be controlled by an

interrupt request bit, an interrupt enable bit, and an interrupt disable flag. In this section, control of inter-

rupts except the BRK instruction interrupt is described and Figure 2.2.5 shows an interrupt control diagram.

Interrupt request bit

Interrupt enable bit

Interrupt disable flag

BRK instruction

Reset

Interrupt request

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