32180 datasheet(93/839 Pages) RENESAS

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4-4

EIT

32180 Group User’s Manual (Rev.1.0)

Operation Result (Content of the Destination Register)

When the DIV0 EIT processing is masked

(Note 1)

When the DIV0 EIT processing is

executed (Note 2)

Nonzero finite value

+-Infinity (Sign is derived by exclusive

ORing the signs of the divisor and

dividend.)

No change

Dividend

Behavior

An invalid operation exception occurs

Infinity

No exceptions occur (with the result = "Infinity")

Note 1: When the zero division exception enable (EZ) bit (FPSR register bit 19) = "0"

Note 2: When the zero division exception enable (EZ) bit (FPSR register bit 19) = "1"

Please note that the DIV0 EIT processing does not occur in the following conditions.

Table 4.2.5 Cases in Which No DIV0 Occur

4.2 EIT Events

3) Inexact Exception (IXCT)

The exception occurs when the operation result differs from a result led out with an infinite range of

precision. The following table shows the operation results and the respective conditions in which each

IXCT occurs.

Table 4.2.3 Operation Results when an IXCT Occurred

Note 1: When the inexact exception enable (EX) bit (FPSR register bit 17) = "0"

Note 2: When the inexact exception enable (EX) bit (FPSR register bit 17) = "1"

4) Zero Division Exception (DIV0)

The exception occurs when a finite nonzero value is divided by zero. The following table shows the

operation results when a DIV0 is occurs.

Table 4.2.4 Operation Results When a DIV0 Occurred

Operation Result (Content of the Destination Register)

When the IXCT EIT processing for is

masked (Note 1)

When the IXCT EIT processing is

executed (Note 2)

Overflow occurs in OVF masked

condition

Reference OVF operation results

No change

Rounding occurs

Rounded value

No change

Occurrence Condition

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