H83297 datasheet(39/393 Pages) RENESAS

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2.4 Addressing Modes

2.4.1 Addressing Mode

The H8/300 CPU supports eight addressing modes. Each instruction uses a subset of these

addressing modes.

Table 2-1 Addressing Modes

No.

Addressing Mode

Symbol

(1)

(2)

@Rn

(3)

@(d:16, Rn)

(4)

@Rn+

@–Rn

(5)

Absolute address

@aa:8 or @aa:16

(6)

Immediate

#xx:8 or #xx:16

(7)

Program-counter-relative

@(d:8, PC)

(8)

Memory indirect

@@aa:8

(1) Register Direct—Rn: The register field of the instruction specifies an 8- or 16-bit general

Only the MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU (8 bits

× 8 bits), and

DIVXU (16 bits ÷ 8 bits) instructions have 16-bit operands.

(2) Register Indirect—@Rn: The register field of the instruction specifies a 16-bit general register

containing the address of the operand.

(3) Register Indirect with Displacement—@(d:16, Rn): This mode, which is used only in MOV

instructions, is similar to register indirect but the instruction has a second word (bytes 3 and 4)

which is added to the contents of the specified general register to obtain the operand address. For

the MOV.W instruction, the resulting address must be even.

(4) Register Indirect with Post-Increment or Pre-Decrement—@Rn+ or @–Rn:

•

The @Rn+ mode is used with MOV instructions that load registers from memory.

It is similar to the register indirect mode, but the 16-bit general register specified in the register

field of the instruction is incremented after the operand is accessed. The size of the increment is

1 or 2 depending on the size of the operand: 1 for MOV.B; 2 for MOV.W. For MOV.W, the

original contents of the 16-bit general register must be even.

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