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74FCT16652ATPVCG4 데이터시트(PDF) 7 Page - Texas Instruments

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부품명 74FCT16652ATPVCG4
상세설명  16-Bit Registered Transceivers
PDF  16 Pages
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제조업체  TI [Texas Instruments]
홈페이지  http://www.ti.com
Logo TI - Texas Instruments

74FCT16652ATPVCG4 데이터시트(HTML) 7 Page - Texas Instruments

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CY74FCT16652T
CY74FCT162652T
7
Switching Characteristics Over the Operating Range[17]
Parameter
Description
CY74FCT16652AT
CY74FCT162652AT
Unit
Min.
Max.
Fig. No.[18]
tPLH
tPHL
Propagation Delay Bus to Bus
1.5
6.3
ns
1, 3
tPZH
tPHL
Output Enable Time OEAB or OEBA to Bus
1.5
9.8
ns
1, 7, 8
tPHZ
tPLZ
Output Disable Time OEAB or OEBA to Bus
1.5
6.3
ns
1, 7, 8
tPLH
tPHL
Propagation Delay Clock to Bus
1.5
6.3
ns
1, 5
tPLH
tPHL
Propagation Delay SBA or SAB to Bus
1.5
7.7
ns
1, 5
tSU
Set-Up time HIGH or LOW Bus to Clock
2.0
ns
4
tH
Hold Time HIGH or LOW Bus to Clock
1.5
ns
4
tW
Clock Pulse Width HIGH or LOW
5.0
ns
5
tSK(O)
Output Skew[19]
0.5
ns
Parameter
Description
CY74FCT16652CT
CY74FCT162652CT
Unit
Min.
Max.
Fig. No.[18]
tPLH
tPHL
Propagation Delay
Bus to Bus
1.5
5.4
ns
1, 3
tPZH
tPHL
Output Enable Time
OEAB or OEBA to Bus
1.5
7.8
ns
1, 7, 8
tPHZ
tPLZ
Output Disable Time
OEAB or OEBA to Bus
1.5
6.3
ns
1, 7, 8
tPLH
tPHL
Propagation Delay
Clock to Bus
1.5
5.7
ns
1, 5
tPLH
tPHL
Propagation Delay
SBA or SAB to Bus
1.5
6.2
ns
1, 5
tSU
Set-Up Time
HIGH or LOW
Bus to Clock
2.0
ns
4
tH
Hold Time
HIGH or LOW
Bus to Clock
1.5
ns
4
tW
Clock Pulse Width
HIGH or LOW
5.0
ns
5
tSK(O)
Output Skew[19]
0.5
ns
Notes:
17. Minimum limits are specified, but not tested, on propagation delays.
18. See “Parameter Measurement Information” in the General Information section.
19. Skew between any two outputs of the same package switching in the same direction. This parameter ensured by design.



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