M38040FDHKP datasheet(89/387 Pages) RENESAS

89 / 387 page

1-71

REJ09B0212-0100Z

Rev.1.00

Jan 14, 2005

3804 Group (Spec.H)

HARDWARE

FUNCTIONAL DESCRIPTION

Fig. 69 Address data communication format

Address Data Communication

There are two address data communication formats, namely, 7-bit

addressing format and 10-bit addressing format. The respective

address communication formats are described below.

➀ 7-bit addressing format

To adapt the 7-bit addressing format, set the 10BIT SAD bit of

the I2C control register (S1D: address 001416) to “0”. The first 7-

bit address data transmitted from the master is compared with

the high-order 7-bit slave address stored in the I2C slave ad-

dress register. At the time of this comparison, address

comparison of the RWB bit of the I2C slave address register is

not performed. For the data transmission format when the 7-bit

addressing format is selected, refer to Figure 69, (1) and (2).

➁ 10-bit addressing format

To adapt the 10-bit addressing format, set the 10BIT SAD bit of

the I2C control register (S1D: address 001416) to “1.” An ad-

dress comparison is performed between the first-byte address

data transmitted from the master and the 8-bit slave address

stored in the I2C slave address register. At the time of this com-

parison, an address comparison between the RWB bit of the

I2C slave address register and the R/W bit which is the last bit

of the address data transmitted from the master is made. In the

10-bit addressing mode, the RWB bit which is the last bit of the

address data not only specifies the direction of communication

for control data, but also is processed as an address data bit.

When the first-byte address data agree with the slave address,

the AAS bit of the I2C status register (S1: address 001316) is

set to “1.” After the second-byte address data is stored into the

I2C data shift register (S0: address 001116), perform an ad-

dress comparison between the second-byte data and the slave

address by software. When the address data of the 2 bytes

agree with the slave address, set the RWB bit of the I2C slave

address register to “1” by software. This processing can make

the 7-bit slave address and R/W data agree, which are re-

ceived after a RESTART condition is detected, with the value of

the I2C slave address register. For the data transmission for-

mat when the 10-bit addressing format is selected, refer to

Figure 69, (3) and (4).

Slave addressR/W

Data

A/A

Data

7 bits

“0”

1 to 8 bits

(1) A master-transmitter transmits data to a slave-receiver

Slave address R/W

Data

7 bits

“1”

1 to 8 bits

(2) A master-receiver receives data from a slave-transmitter

7 bits

“0”

8 bits

(3) A master-transmitter transmits data to a slave-receiver with a 10-bit address

1 to 8 bits

R/W

Slave address

1st 7 bits

Slave address

2nd bytes

AData

Data

A/A

7 bits

“0”

8 bits

(4) A master-receiver receives data from a slave-transmitter with a 10-bit address

S : START condition

A : ACK bit

Sr : Restart condition

P : STOP condition

R/W : Read/Write bit

7 bits

“1”

1 to 8 bits

R/W

Slave address

1st 7 bits

Slave address

2nd bytes

Slave address

1st 7 bits

R/W

Data

: Master to slave

: Slave to master

M38040FDHKP 데이터시트(PDF) 89 Page - Renesas Technology Corp

M38040FDHKP 데이터시트(HTML) 89 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL