 |
전자부품 데이터시트 검색엔진 |
|
|
전자부품 데이터시트 검색엔진 |
|
M38040FDHKP 데이터시트(PDF) 236 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
M38040FDHKP 데이터시트(HTML) 236 Page - Renesas Technology Corp |
|
|
236 / 387 page  2-112 APPLICATION 2.5 Multi-master I2C-BUS interface Rev.1.00 Jan 14, 2004 REJ09B0212-0100Z 3804 Group (Spec.H) ➄ Transmission of upper data Confirm correct completion of the upper data transmission. The master returns the NACK toward the transmitted second-byte data, the upper data. Accordingly, confirm that the last receive bit (LRB bit; bit 0 of address 001316) is “1”. After that, write dummy data to the I2C data shift register and wait for the interrupt of STOP condition. Fig. 2.5.33 Transmission process of upper data End S0 (address 001116) ← 111111112 Error end 0 (ACK) LRB (address 001316), bit 0 ? 1 (NACK) 5 PIN (address 001316), bit 4 ? 1 (STOP condition) 0 (upper data transmission completed) S1 (address 001316) ← 000100002 Note: Use the branch bit instruction to check bus busy. • Judgment of bus hold • ACK confirmation • Slave receive mode set • Dummy data write to I2C data shift register |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Korean ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
