M38042FDHKP datasheet(35/387 Pages) RENESAS

35 / 387 page

1-17

REJ09B0212-0100Z

Rev.1.00

Jan 14, 2005

3804 Group (Spec.H)

HARDWARE

FUNCTIONAL DESCRIPTION

Fig. 13 Port block diagram (2)

(10) Port P40

(11) Port P41

(13) Port P50

Port XC switch bit

INT40 interrupt input

Port P41

Serial I/O2 input

(12) Port P47

(9) Port P37

SRDY3 output enable bit

(14) Port P51

INT00 interrupt input

Serial I/O3 enable bit

Serial I/O3 mode

selection bit

Data bus

Direction

Port latch

Pull-up control bit

Serial I/O3 ready output

Pull-up control bit

Data bus

Direction

Port latch

Port XC switch bit

Oscillator

CNTR2 interrupt input

SRDY1 output enable bit

Serial I/O1 enable bit

Serial I/O1 mode selection bit

Data bus

Serial I/O1 ready output

Timer output

Data bus

Direction

Port latch

Pull-up control bit

Sub-clock generating circuit input

Port XC switch bit

Pull-up control bit

Data bus

Direction

Port latch

Pull-up control bit

Data bus

Direction

Port latch

Serial I/O2 output

Serial I/O2 transmit completion signal

Serial I/O2 port selection bit

P-channel output

disable bit

Bit 2

Timer Z operating

mode bits

Bit 1

Bit 0

Port latch

Direction

Pull-up control bit

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