M38048FDHKP datasheet(225/387 Pages) RENESAS

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2-101

APPLICATION

2.5 Multi-master I2C-BUS interface

Rev.1.00 Jan 14, 2005

REJ09B0212-0100Z

3804 Group (Spec.H)

➀ Generating of START condition; Transmission of slave address + write bit

After confirming that other master devices do not use the bus, generate the START condition,

because the SMBUS is a multi-master.

Write “slave address + write bit” to the I2C data shift register (address 001116) before performing

to make the START condition generate. It is because the SCL of 1-byte unit is output, following

occurrence of the START condition.

If other master devices start communication until an occurrence of the START condition after

confirming the bus use, it cannot communicate correctly. However in this case, that situation does

not affect other master devices owing to detection of an arbitration lost or the START condition

duplication preventing function.

Fig. 2.5.22 Generating of START condition and transmission process of slave address + write bit

BB (address 001316), bit5 ? (Note 2)

0 (not used)

1 (used)

End

(A)

←000100002

SEI (Note 1)

S0 (address 001116)

← (A)

S1 (address 001316)

←111100002

CLI (Note 1)

• Interrupts disabled

• Bus use confirmation

• START condition occurrence

• Slave address value write

• Interrupt enabled

Notes 1: In this example, the SEI instruction to disable interrupts need not be executed

because this processing is going to be performed in the interrupt processing.

When the START condition is generated out of the interrupt processing, execute

the SEI instruction to disable interrupts.

2: Use the branch bit instruction to confirm bus busy.

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