M38048FDHKP datasheet(228/387 Pages) RENESAS

228 / 387 page

2-104

APPLICATION

2.5 Multi-master I2C-BUS interface

Rev.1.00 Jan 14, 2005

REJ09B0212-0100Z

3804 Group (Spec.H)

➃ Reception of lower data

Confirm correct completion of communication at ➂ before receiving the lower data. After confirming

correct completion, clear the ACK bit (bit 6 of address 001516) to “0”, in which ACK is returned,

and set to the master receive mode. After that, write dummy data to the I2C data shift register

(address 001116).

When the MST bit (bit 7 of address 001316) is “0”, perform the error process explained as follows

and return to the process ➀.

When the last receive bit (LRB bit; bit 0 of address 001316) is “1”, generate the STOP condition

and make the bus release, because the slave device specified on the SMBUS does not exist.

Fig. 2.5.25 Reception process of lower data

1 (STOP condition)

AL (address 001316), bit 3 ?

MST (address 001316), bit 7 ?

0 (ACK)

1 (master)

S2 (address 001516)

← 100001012

LRB (address 001316), bit 0 ?

0 (slave)

1 (NACK)

1 (detected)

0 (not detected)

End

Re-transmission preparation

Error processing

S1 (address 001316)

←101000002

S0 (address 001116)

← 111111112

PIN (address 001316), bit 4 ?

0 (transmission of RESTART

condition)

• Master receive mode set

STOP condition output

• Judgment of bus hold

• Judgment of arbitration lost detection

• ACK confirmation

• “ACK clock is used” select and

“ACK is returned” set

• Judgment of slave mode detection

• Dummy data to I2C data shift register write

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