APPLICATION INFORMATION

SERIAL BUS INTERFACE

The serial bus interface is compatible to SPI bus

systems.

During the LOW state of the chip enable signal

(CE) the data on pin DA are clocked into the shift

register at the LOW to HIGH transition of the

clock signal CL.

At the LOW to HIGH transition of the CE signal

the content of the internal shift register is stored

into the addressed latches.

The transmission is separated into bytes with 8 bit

according to the data specification of the audio-

processor. After every byte a positive slope of the

CE signal has to be generated in order to store

the data byte.

A special clock counter enables the latch of the

data byte only, if exactly 8 clocks were present

during the LOW state of the CE signal. This re-

sults in a high immunity against spikes on the

clock line and avoids a storage of wrong databy-

tes.

Figure 1: BUS Timing

Nr.

Parameter

Min.

Max.

Units

Clock Frequency

250

KHz

1

CE Lead time

4

µs

2

Clock High Time

2

µs

3

Clock Low Time

2

µs

4

Data Hold Time

1.8

µs

5

Data Setup Time

1.8

µs

6

Clock Setup Time

0

µs

7

CE lagtime

0

µs

8

Clock Hold Time

6

µs

9

CE High TIme

6

µs

TDA7311

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