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TDA7340G 데이터시트(PDF) 19 Page - STMicroelectronics |
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TDA7340G 데이터시트(HTML) 19 Page - STMicroelectronics |
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19 / 27 page ![]() VPEAK (V) D95AU332A 20 DEVIATION(KHz) 0.9 1.3 2.3 3.2 DETECTOR OFF (11) 32.5 45 75 OVM=10 OVM=01 OVM=00 Figure 7: Behaviour of the Deviation Dependent Threshold Adiust (Over Deviation Detector) 2.2V(00) TRIG. THRESHOLD 0.9V VPEAK E’ D95AU333A 1.8V(01) 1.2V(10) MONO STEREO noisy signal good signal ATC_SB OFF (11) NOISE ≈3V Figure 6: Behaviour of the Field Strength Controlled Threshold Adjustment MUTE & PAUSE FEATURES The TDA7340G provides three types of mute, controlled via I2C bus (see pag.12, MUTE BYTE register). SOFT MUTE Bit D0=1 → Soft Mute ON Bit D0=0 →Soft Mute OFF It allows an automatic soft muting and unmuting of the signal. The time constant is fixed by an external capaci- tor Csm inserted between pin Csm and ground. Once fixed the external capacitor, two different slopes (time constant) are selectable by program- mation of bit D1. Bit D1=1 → fast slope (I=Imax) Bit D1=0 → slow slope (I=Imin) The soft mute generates a gradual signal de- creasing avoiding big click noise of an immediate high attenuation, without necessity to program a sequence of decreasing volume levels. A re- sponse example is reported in Fig.12 (mute) and Fig.13 (unmute). The final attenuation obtained with soft mute ON is 60dB typical. The used reference parameter is the delay time taken to reach 20dB attenuation (no matter what the signal level is). Using a capacitor Csm=22nF this delay is: d = 1. 8ms when selected Fast slope mode (bit D1=1) d = 25 ms when selected Slow slope mode (bit D1=0) TDA7340G 19/27 |
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