AD5722/AD5732/AD5752

Rev. 0 | Page 24 of 32

INPUT SHIFT REGISTER

The input shift register is 24 bits wide and consists of a read/write bit (R/W

Table 16. Input Register Format

), a reserved bit (zero) that must always be set to 0, three

register select bits (REG0, REG1, REG2), three DAC address bits (A2, A1, A0), and 16 data bits (data). The register data is clocked in MSB

first on the SDIN pin. Table 16 shows the register format, and Table 17 describes the function of each bit in the register. All registers are

read/write registers.

MSB

LSB

DB23

DB22

DB21

DB20

DB19

DB18

DB17

DB16

DB15 to DB0

R/W

Zero

REG2

REG1

REG0

A2

A1

A0

Data

Table 17. Input Register Bit Functions

Bit Mnemonic

Description

R/W

Indicates a read from or a write to the addressed register.

REG2, REG1, REG0

Used in association with the address bits to determine if a write operation is to the DAC register, the output range

select register, the power control register, or the control register.

REG2

REG1

REG0

Function

0

0

0

DAC register

0

0

1

Output range select register

0

1

0

Power control register

0

1

1

Control register

A2, A1, A0

These DAC address bits are used to decode the DAC channels.

A2

A1

A0

Channel Address

0

0

0

DAC A

0

1

0

DAC B

1

0

0

Both DACs

Data

Data bits.