DSP56724 datasheet(21/48 Pages) FREESCALE

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Symphony™ DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 1

Freescale Semiconductor

Start condition hold time

THD;STA

4.0

—

0.6

—

μs

SCL low period

TLOW

4.7

—

1.3

—

μs

SCL high period

THIGH

4.0

—

1.3

—

μs

SCL and SDA rise time7

—

1000

—

300

SCL and SDA fall time7

—5.0

—

5.0

Data set-up time

TSU;DAT

250

—

100

—

Data hold time

THD;DAT

0.0

—

0.0

0.9

μs

DSP clock frequency

• Filters bypassed

• Very Narrow filters enabled

• Narrow filters enabled

• Wide filters enabled

FOSC

10.6

11.8

13.1

—

28.5

39.7

61.0

—

MHz

SCL low to data out valid

TVD;DAT

—3.4

—

0.9

μs

Stop condition setup time

TSU;STO

4.0

—

0.6

—

μs

HREQ in deassertion to last SCL edge (HREQ in

set-up time)

tSU;RQI

0.0

—

0.0

—

First SCL sampling edge to HREQ output

deassertion2

• Filters bypassed

• Very Narrow filters enabled

• Narrow filters enabled

• Wide filters enabled

TNG;RQO

× T

C + 30

× T

C + 50

× T

C + 130

× T

C + 230

—

50.0

70.0

250.0

150.0

—

50.0

70.0

150.0

250.0

Last SCL edge to HREQ output not deasserted2

• Filters bypassed

• Very Narrow filters enabled

• Narrow filters enabled

• Wide filters enabled

TAS;RQO

× T

C + 30

× T

C + 40

× T

C + 80

× T

C + 130

140

—

140

—

Table 10. SHI I2C Protocol Timing (Continued)

Standard I2C

No.

Characteristics1,2,3,4,5

Symbol/

Expression

Standard

Fast-Mode

Unit

Min

Max

Min

Max

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