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AD9520-4/PCBZ 데이터시트(PDF) 46 Page - Analog Devices

부품명 AD9520-4/PCBZ
상세설명  12 LVPECL/24 CMOS Output Clock Generator with Integrated 1.6 GHz VCO
PDF  84 Pages
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AD9520-4/PCBZ 데이터시트(HTML) 46 Page - Analog Devices

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AD9520-4
Rev. 0 | Page 46 of 84
Duty-cycle correction requires the following channel divider
conditions:
• An even division must be set as M = N
• An odd division must be set as M = N + 1
When not bypassed or corrected by the DCC function, the duty
cycle of each channel divider output is the numerical value of
(N + 1)/(N + M + 2) expressed as a percent.
The duty cycle at the output of the channel divider for various
configurations is shown in Table 35 to Table 38.
Table 35. Channel Divider Output Duty Cycle with VCO
Divider ≠ 1, Input Duty Cycle Is 50%
VCO
Divider
DX
Output Duty Cycle
N + M + 2
Disable Divider
DCC = 1
Disable Div
DCC = 0
Even
Channel
divider
bypassed
50%
50%
Odd = 3
Channel
divider
bypassed
33.3%
50%
Odd = 5
Channel
divider
bypassed
40%
50%
Even, odd
Even
(N + 1)/(N + M + 2)
50%; requires
M = N
Even, odd
Odd
(N + 1)/(N + M + 2)
50%; requires
M = N + 1
Table 36. Channel Divider Output Duty Cycle with VCO
Divider ≠ 1 and Input Duty Cycle Is X%
VCO
Divider
DX
Output Duty Cycle
N + M + 2
Disable Div
DCC = 1
Disable Div DCC = 0
Even
Channel
divider
bypassed
50%
50%
Odd = 3
Channel
divider
bypassed
33.3%
(1 + X%)/3
Odd = 5
Channel
Divider
bypassed
40%
(2 + X%)/5
Even
Even
(N + 1)/
(N + M + 2)
50%, requires M = N
Even
Odd
(N + 1)/
(N + M + 2)
50%, requires M = N + 1
Odd = 3
Even
(N + 1)/
(N + M + 2)
50%, requires M = N
Odd = 3
Odd
(N + 1)/
(N + M + 2)
(3N + 4 + X%)/(6N + 9),
requires M = N + 1
Odd = 5
Even
(N + 1)/
(N + M + 2)
50%, requires M = N
Odd = 5
Odd
(N + 1)/
(N + M + 2)
(5N + 7 + X%)/(10N + 15),
requires M = N + 1
Table 37. Channel Divider Output Duty Cycle When the
VCO Divider is Enabled and Set to 1
Input
Clock
Duty Cycle
DX
Output Duty Cycle
N + M + 2
Disable Div
DCC = 1
Disable Div DCC = 0
Any
Even
(N + 1)/
(M + N + 2)
50%, requires M = N
50%
Odd
(N + 1)/
(M + N + 2)
50%, requires M = N + 1
X%
Odd
(N + 1)/
(M + N + 2)
(N + 1 + X%)/(2 × N + 3),
requires M = N + 1
Note Channel Divider must be enabled when VCO Divider = 1.
Table 38. Channel Divider Output Duty Cycle When the
VCO Divider Is Bypassed
Input
Clock
Duty Cycle
DX
Output Duty Cycle
N + M + 2
Disable Div
DCC = 1
Disable Div DCC = 0
Any
Chanel
divider
bypassed
Same as input
duty cycle
Same as input duty
cycle
Any
Even
(N + 1)/
(M + N + 2)
50%, requires M = N
50%
Odd
(N + 1)/
(M + N + 2)
50%, requires M = N + 1
X%
Odd
(N + 1)/
(M + N + 2)
(N + 1 + X%)/(2 × N + 3),
requires M = N + 1
The internal VCO has a duty cycle of 50%. Therefore, when the
VCO is connected directly to the output, the duty cycle is 50%.
If the CLK input is routed directly to the output, the duty cycle of
the output is the same as the CLK input.
Phase Offset or Coarse Time Delay
Each channel divider allows for a phase offset, or a coarse time
delay, to be programmed by setting register bits (see Table 39).
These settings determine the number of cycles (successive rising
edges) of the channel divider input frequency by which to offset, or
delay, the rising edge of the output of the divider. This delay is
with respect to a nondelayed output (that is, with a phase offset
of zero). The amount of the delay is set by five bits loaded into
the phase offset (PO) register plus the start high (SH) bit for
each channel divider. When the start high bit is set, the delay is
also affected by the number of low cycles (M) programmed for
the divider.
It is necessary to use the SYNC function to make phase offsets
effective (see the Synchronizing the Outputs—SYNC Function
section.)
Table 39. Setting Phase Offset and Division
Divider
Start
High (SH)
Phase
Offset (PO)
Low Cycles
M
High Cycles
N
0
0x191[4]
0x191[3:0]
0x190[7:4]
0x190[3:0]
1
0x194[4]
0x194[3:0]
0x193[7:4]
0x193[3:0]
2
0x197[4]
0x197[3:0]
0x196[7:4]
0x196[3:0]
3
0x19A[4]
0x19A[3:0]
0x199[7:4]
0x199[3:0]



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