AD9522-2SLASHPCBZ datasheet(47/84 Pages) AD

47 / 84 page

AD9522-2

Rev. 0 | Page 47 of 84

910

INPUT TO VCO DIVIDER

INPUT TO CHANNEL DIVIDER

OUTPUT OF

CHANNEL DIVIDER

SYNC PIN

14 TO 15 CYCLES AT CHANNEL DIVIDER INPUT + 1 CYCLE AT VCO DIVIDER INPUT

CHANNEL DIVIDER OUTPUT STATIC

CHANNEL DIVIDER

OUTPUT CLOCKING

CHANNEL DIVIDER

OUTPUT CLOCKING

Figure 52. SYNC Timing Pipeline Delay When the VCO Divider Is Used—CLK or VCO Is Input

INPUT TO CLK

INPUT TO CHANNEL DIVIDER

OUTPUT OF

CHANNEL DIVIDER

SYNC PIN

14 TO 15 CYCLES AT CHANNEL DIVIDER INPUT + 1 CYCLE AT CLK INPUT

910

CHANNEL DIVIDER OUTPUT STATIC

CHANNEL DIVIDER

OUTPUT CLOCKING

CHANNEL DIVIDER

OUTPUT CLOCKING

Figure 53. SYNC Timing Pipeline Delay When the VCO Divider Is Not Used—CLK Input Only

LVDS Output Drivers

The AD9522 output drivers can be configured as either an

LVDS differential output or as a pair of CMOS single-ended

outputs. The LVDS outputs allow for selectable output current

from ~1.75 mA to ~7 mA.

The LVDS output polarity can be set as noninverting or

inverting, which allows for the adjustment of the relative

polarity of outputs within an application without requiring a

board layout change. Each LVDS output can be individually

powered down to save power.

OUT

3.5mA

Figure 54. LVDS Output Simplified Equivalent Circuit with

3.5 mA Typical Current Source

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