AD9522-5SLASHPCBZ datasheet(37/76 Pages) AD

37 / 76 page

AD9522-5

Rev. 0 | Page 37 of 76

DIVIDE BY 1,

2, 3, 4, 5, OR 6

EXTERNAL VCXO

CLK/CLK

DIVIDER

DELAY

DIVIDER

DELAY

PFD

MUX1

REG 0x01E[1] = 1

REFIN/

REFIN

INTERNAL ZERO DELAY CLOCK FEEDBACK PATH

CHANNEL DIVIDER 0

CHANNEL DIVIDER 1

CHANNEL DIVIDER 2

CHANNEL DIVIDER 3

OUT0 TO OUT2

OUT3 TO OUT5

OUT6 TO OUT8

OUT9 TO OUT11

AD9522-5

LOOP

FILTER

Figure 36. Zero Delay Function

ZERO DELAY OPERATION

Because the channel dividers are synchronized to each other,

the outputs of the channel dividers are synchronous with the

reference input. Both the R delay and the N delay inside the

PLL can be programmed to compensate for the propagation

delay from the output drivers and PLL components to minimize

the phase offset between the clock output and the reference

input to achieve zero delay.

Zero delay operation aligns the phase of the output clocks with

the phase of the external PLL reference input.

The zero delay function of the AD9522-5 is achieved by feeding

the output of Channel Divider 0 back to the PLL N divider. In

Figure 36, the change in signal routing for zero delay mode is

shown in blue.

Set Register 0x01E[1] = 1b to select the zero delay mode. In the

zero delay mode, the output of Channel Divider 0 is routed back to

the PLL (N divider) through MUX1 (feedback path shown in blue

in Figure 36). The PLL synchronizes the phase/edge of the output

of Channel Divider 0 with the phase/edge of the reference input.

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