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ADATE304BBCZ 데이터시트(PDF) 41 Page - Analog Devices

부품명 ADATE304BBCZ
상세설명  200 MHz Dual Integrated DCL with Level Setting DACs, Per Pin PMU, and Per Chip VHH
PDF  52 Pages
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ADATE304
Rev. 0 | Page 41 of 52
USER INFORMATION
POWER SUPPLY CONSIDERATIONS
Power Supply Sequencing
It is recommended that the power supplies be brought up in the
following order:
1.
Grounds (DGND, AGND, VREF_GND)
2.
VSS
3.
VCC, VCOMP_VTT, and VREF
4.
VDD
5.
VPLUS
If the HVOUT pin is not used, the VPLUS supply can be
connected to VDD.
Power Supply Decoupling
The ADATE304 is a high performance device that requires
close attention to power supply decoupling to deliver the best
performance. The use of full power planes with low inductance
capacitors placed as close to the power pins as possible is recom-
mended. The following power connections are the most important:
•
VPLUS to AGND (for the HVOUT driver)
•
VDD to VSS near the DUTx pin (for the driver)
•
VDD and VSS to AGND near the DUTx pin (for the
comparators)
•
VCC to DGND (for the digital)
Additionally, large bulk capacitors (that is, 10 μF) should be
used on every power supply on the printed circuit board (PCB).
TRUTH TABLES
Table 29. Driver and Load Truth Table1
Registers
Signals
Driver State
Load State
PE Disable
DATA[0]
ADDR[4:0] = 0x0C
Force VT
DATA[1]
ADDR[4:0] = 0x0C
Load Enable
DATA[1]
ADDR[4:0] = 0x0D
Driver High-Z/VT
DATA[0]
ADDR[4:0] = 0x0D
DATAx
RCVx
1
X
X
X
X
X
High-Z without clamps
Power-down
0
1
X
X
X
X
VT
Power-down
0
0
0
0
0
0
VL
Power-down
0
0
0
0
0
1
High-Z with clamps
Power-down
0
0
0
0
1
0
VH
Power-down
0
0
0
0
1
1
High-Z with clamps
Power-down
0
0
0
1
0
0
VL
Power-down
0
0
0
1
0
1
VT
Power-down
0
0
0
1
1
0
VH
Power-down
0
0
0
1
1
1
VT
Power-down
0
0
1
0
0
0
VL
Active off
0
0
1
0
0
1
High-Z with clamps
Active on
0
0
1
0
1
0
VH
Active off
0
0
1
0
1
1
High-Z with clamps
Active on
0
0
1
1
0
0
VL
Active on
0
0
1
1
0
1
High-Z with clamps
Active on
0
0
1
1
1
0
VH
Active on
0
0
1
1
1
1
High-Z with clamps
Active on
1 X means don’t care.
Table 30. HVOUT Truth Table1
HVOUT Mode Select
DATA[2]
ADDR[4:0] =0x0D
Channel 0
RCV
Channel 0
DATA
HVOUT Driver Output
1
1
X
VHH mode; VHH = (VT + 1 V) × 2 + DUTGND (Channel 0 VT DAC)
1
0
0
VL (Channel 0 VL DAC)
1
0
1
VH (Channel 0 VH DAC)
0
X
X
Disabled (HVOUT pin set to 0 V low impedance)
1 X means don’t care.



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