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ADATE305 데이터시트(PDF) 49 Page - Analog Devices

부품명 ADATE305
상세설명  250 MHz Dual Integrated DCL with Level Setting DACs, Per Pin PMU, and Per Chip VHH
PDF  56 Pages
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ADATE305 데이터시트(HTML) 49 Page - Analog Devices

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ADATE305
Rev. 0 | Page 49 of 56
BLOCK DIAGRAMS
RCV
VT
VCL
VCH
DATA
VH
VL
V(IOL)
V(IOH)
DUT
DRIVER HIGH-Z/VT DATA[0]
(ADDR[4:0] = 0x0D)
VT BUFFER WHEN 1
HIGH-Z BUFFER WHEN 0
FORCE VT DATA[1] (ADDR[4:0] = 0x0C)
OVERRIDES THE RCV PIN AND FORCES
VTERM MODE ON THE DRIVER AND LOAD
POWER-DOWN MODE
LOAD ENABLE DATA[1] (ADDR[4:0] = 0x0D)
FORCES SWITCHES OPEN AND POWERS
DOWN LOAD WHEN 0
PE DISABLE DATA[0] (ADDR[4:0] = 0x0C)
FORCES SWITCH OPEN WHEN 1
ROUT = 47Ω
(TRIMMED)
DRIVER
VCOM
Figure 79. Driver and Load Block Diagram
48Ω
VL
DATA
RCV (SHOWN IN
RCV = 0 STATE)
VHH = (VT + 1V) × 2 + DUTGND
VH
~5Ω
HV MODE SELECT DATA[2]
(ADDR [4:0] = 0x0D) DISABLES
HV DRIVER AND FORCES
0V ON HVOUT WHEN 0
HVOUT
Figure 80. HVOUT Driver Output Stage



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