TS68HC901 datasheet(28/42 Pages) STMICROELECTRONICS

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TSR

(2Dh)

END

Figure 19 :

USART error conditions are only valid for each character boundary. When the USART performs block

data transfers by using the DMA handshake line RR (receiver ready) and TR (transmitter ready), errors

must be saved and checked at the end of a block. This is accomplished by enabling the error channel

for the receiver or transmitter and by masking interrupts for this channel. Once the transfer is complete,

interrupt pending register A is read. Any pending receiver or transmitter error indicates an error in the

data transfer.

Buffer Empty. This bit is set when the word in the transmit buffer is transferred to the transmit

shift register. This bit is cleared when the transmit buffer is reloaded by writing to the USART

data register (UDR).

SET : Transmit buffer contents transferred to transmit shift register

CLEARED : Transmit buffer written

Underrun Error. This bit is set when the word in the transmit shift register has been transmitted

before a new word is loaded into the transmit buffer. This bit is cleared by reading the TSR

or by disabling the transmitter. This bit does not need to be cleared before writing to the UDR.

SET : Transmit shift register contents transmitted before transmit buffer written

CLEARED : Transmitter status register read or Transmitter disabled

Auto-Turnaround. When this bit is set, the receiver will be enabled automatically after the

transmitter has been disabled and the last character being transmitted is completed.

SET : MPU writes a one

CLEARED : Transmitter disabled

END

End of Transmission. When the transmitter is disabled while a character is being transmitted,

the END will be set after the character transmission is complete. If no word is being transmitted

when the transmitter is disabled, the END bit will be set immediately. The END bit is cleared

by reenabling the transmitter.

SET : Transmitter disabled

CLEARED : Transmitter enabled

Break. This bit has no function in the

synchronous character format. In the

asynchronous character format, when

this bit is set to a one, a break will be

transmitted upon the completion of the

transmission of any word in the trans-

mit shift register. A break consists of an all zero data word with no stop bit. When this bit is

cleared by software, the break indication will cease and normal transmission will resume. Note

that when B is set, BE cannot be set.

SET : MPU writes a one

CLEARED : MPU writes a zero

H, L

High and Low. These control bits configure the transmitter output (SO) when the transmitter

is disabled. These bits also force the transmitter output after the transmitter is enabled until

END is cleared.

Loopback mode internally connects the transmitter output to the receiver input and the trans-

mitter clock to the receiver clock internally. The receiver clock (RC) and the serial input (SI)

are not used. When the transmitter is disabled, SO is forced high.

SET : MPU writes a one

Output

High Impedance

LOW

High

Loopback Mode

TS68HC901

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