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PRELIMINARY
CY2DP818-2
Document #: 38-07588 Rev. *A
Page 3 of 9
Power Supply Characteristics
Parameter
Description
Test Conditions
Min Typ Max
Unit
ICCD
Dynamic Power Supply Current
VDD = Max.
Input toggling 50% Duty Cycle, Outputs Open
1.5
2.0
mA/
MHz
IC
Total Power Supply Current
VDD = Max.
Input toggling 50% Duty Cycle, Outputs 50 ohms,
fL=100 MHz
350
mA
IC Core
Core Current when Output Loads
are Disabled
VDD = Max.
Input toggling 50% Duty Cycle, Outputs Disabled,
not connected to VTT fL = 100 MHz
50
mA
Input Receiver Configuration for Differential or LVTTL/LVCMOS
INCONFIG Pin 7
Binary Value
Input Receiver Family
Input Receiver Type
1
LVTTL in LVCMOS
Single ended, non inverting, inverting, void of bias resistors
0
LVDS
Low voltage differential signaling
LVPECL
Low voltage pseudo (positive) emitter coupled logic
Function Control of the TTL Input Logic used to Accept or Invert the Input Signal
LVTTL/LVCMOS Input Logic
Input Condition
Input Logic
Output Logic Q Pins, Q1A or Q1
Ground
Input B (–) Pin 11
Input A (+) Pin 10
Input
True
VDD
Input B (–) Pin 11
Input A (+) Pin 10
Input
Invert
Ground
Input A (+) Pin 10
Input B (–) Pin 11
Input
Invert
VDD
Input A (+) Pin 10
Input B (–) Pin 11
Input
True
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