PCA2003 datasheet(8/21 Pages) NXP

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PCA2003_1

Product data sheet

Rev. 01 — 15 December 2008

8 of 21

NXP Semiconductors

PCA2003

32 kHz watch circuit with programmable adaptive motor pulse

Table 4.

Words and bits

Word

Bit

number of 8192 Hz pulses to be removed

calibration

period

lowest stage: duty cycle

number of driving stages

highest

stage: duty

cycle

pulse

stretching

output period

pulse width

maximum time delay between positive

and negative detection pulses

output

period

factory test

bit

type

factory test bits

Table 5.

Description of word A bits

Bit

Value

Description

Inhibition time

1 to 7

adjust the number of the 8192 Hz pulses to be removed;

bit 1 is the MSB and bit 7 is the LSB

Calibration period

1 minute

2 minute

Table 6.

Description of word B bits

Bit

Value

Description

Duty cycle lowest driving stage

1 to 2

37.5 %

43.75 %

50 %

56.25 %

Number of driving stages

3 to 4

6[1]

Duty cycle highest driving stage

75 %[2]

100 %

Pulse stretching

no pulse stretching

pulse of 2

× tp and duty cycle of 25 % are added

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