PCF8534AUSLASHDASLASH1 datasheet(19/44 Pages) NXP

19 / 44 page

PCF8534A_3

Product data sheet

Rev. 03 — 10 November 2008

19 of 44

NXP Semiconductors

PCF8534A

Universal LCD driver for low multiplex rates

8.1.1.1

START and STOP conditions

Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW change

of the data line, while the clock is HIGH, is deﬁned as the START condition (S).

A LOW-to-HIGH change of the data line, while the clock is HIGH, is deﬁned as the STOP

condition (P). The START and STOP conditions are illustrated in Figure 13.

8.1.2 System conﬁguration

A device generating a message is a ‘transmitter’ and a device receiving a message is the

‘receiver’. The device that controls the message is the ‘master’ and the devices which are

controlled by the master are the ‘slaves’. The system conﬁguration is illustrated in

Figure 14.

8.1.3 Acknowledge

The number of data bytes transferred between the START and STOP conditions from

transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge

bit. The acknowledge bit is a HIGH level signal put on the bus by the transmitter during

which time the master generates an extra acknowledge related clock pulse.

Fig 12. Bit transfer

mba607

data line

stable;

data valid

change

of data

allowed

SDA

SCL

Fig 13. Deﬁnition of START and STOP conditions

mbc622

SDA

SCL

STOP condition

SDA

SCL

START condition

Fig 14. System conﬁguration

mga807

SDA

SCL

MASTER

TRANSMITTER/

RECEIVER

MASTER

TRANSMITTER

SLAVE

TRANSMITTER/

RECEIVER

SLAVE

RECEIVER

MASTER

TRANSMITTER/

RECEIVER

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